An ESD protection circuit used in an integrated circuit (IC) is a circuit designed to protect other circuitry (e.g., host circuit) on the IC from being damaged by an ESD event. Generally, an ESD event is a single-event, rapid transfer of electrostatic charge between two objects, usually resulting when two objects at different potentials come into direct contact with one another. ESD can also occur when a high electrostatic field develops between two objects in close proximity. ESD is one of the major causes of device failures in the semiconductor industry.
An ESD protection circuit is typically directly coupled to the host circuit to be protected but remains turned off until triggered by the ESD event. Although the ESD protection circuit is preferably turned off during normal operation of the host circuit, the ESD protection circuit includes parasitic elements which can adversely impact the operation and performance of the host circuit, such as, for example, via parasitic loading of input and/or output nodes in the host circuit. Furthermore, parasitic loading attributable to the ESD protection circuit is not easily modeled and simulated, thereby making it difficult to predict the impact of the ESD protection circuit on host circuit performance.
Accordingly, there exists a need for an improved ESD protection circuit that does not suffer from one or more of the above-described problems associated with conventional ESD protection circuitry.